Synchronous up/down counters

1. Synchronous up/down counters count number of pulses applied on the clock input. They consist of flip-flops and steering logic.

2. The reversible counters have the; following inputs and outputs: clock pulses inputs for counting down and counting up; clear input for resetting counter at any time; data and load inputs for presetting counter to desirable initial number before counting of clock pulses; data out puts for indicating in binary code current number in counter; carry output for indicating overflow of counter and borrow output for indicating underflow of counter. 

3. The outputs of all flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count in put is pulsed while the other count input is high.

4. Counters are fully programmable, that is each output may be preset to either level by entering the desired data at the data inputs while the load input is low.

5. The output will change to agree with data inputs independently of the count pulses. This feature allows the counters to be used as module-N dividers by simply modifying the count length with preset inputs.

6. A clear input forces all outputs to the low level when a low level is applied to this input. The clear function is independent of the count and load inputs.

7. The counters are designed to be cascaded. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse when the counter underflows. Similarly the carry output produces a pulse when overflow occurs.

8. The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.